[Oral Presentation]Inclusive Performance Analysis Of 100 Gbps PAM-4 at SerDes Using Digital Equalizers

Inclusive Performance Analysis Of 100 Gbps PAM-4 at SerDes Using Digital Equalizers

ID：56 Submission ID：151 View Protection：ATTENDEE Updated Time：2024-08-08 15:52:15 Hits：19 Oral Presentation

Start Time：2024-10-25 15:45 （Asia/Bangkok）

Duration：15min

Session：[RS1] Regular Session 1 » [RS1-1] Mobile computing, communications, 5G and beyond

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Abstract

In recent years we have witnessed an increase in data transfer rates, which requires the development of new communication methods that can handle high-speed data transfer at challenging communication channels. One of the needs is the transmission of communication over serializer deserializer (SerDes) printed circuit boards (PCBs). which are used to transmit data between chips at high speeds of 10 Gb/s and above, using the Pulse Amplitude Modulation with Four Levels (PAM-4) encoding method, which enables lower losses and relatively low cost.
There is significant signal degradation in high-speed communication systems at SerDes, and the inter-symbol interference (ISI) distortion dominates. One of the most effective methods to mitigate ISI distortion is the use of equalizers.
The goal of this research is to study the performance of communication between two chips (transmitter/receiver) over SerDes PCB at 100 Gbs using the PAM-4 encoding method with an integrated continuous time linear equalizer (CTLE), feedforward equalizer (FFE) and decision feedback equalizer (DFE).
The analysis includes a transmitter/receiver with PAM-4 encoding in a simulation environment combined with lab measurements that obtain the PCB channel response. Further, testing the performance of the combination of different equalizers while defining relevant values and parameters (rate, transmission, convergence rate, and equalizer coefficients). Performance are evaluated using signal-to-noise ratio (SNR) and bit error rate probability (BER) metrics.
We investigated the BER performance for five PCBs of different lengths with analog CTLE and digital FFE-DFE equalizers and found that:
For a small number of taps in FFE-DFE, a specific CTLE configuration is optimal, but for an optimal combination of FFE-DFE, a different configuration of the CTLE is the best for all PCB lengths.
We also show that the longer the PCB length, the more coefficients of the CTLE are needed, consequently, more power is required to compensate for a longer PCB length.